1. Field of the Invention
The present invention generally relates to deposition of a metal layer onto a substrate. More particularly, the present invention relates to an apparatus and a method for electroplating a metal layer onto a substrate.
2. Background of the Related Art
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increases, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceed 2:1, and particularly where it exceeds 4:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, sub-micron features having high aspect ratios.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum's low electrical resistivity, its superior adhesion to silicon dioxide (SiO2), its ease of patterning, and the ability to obtain it in a highly pure form. However, aluminum has a higher electrical resistivity than other more conductive metals such as copper and silver, and aluminum also can suffer from electromigration phenomena. Electromigration is considered as the motion of atoms of a metal conductor in response to the passage of high current density through it, and it is a phenomenon that occurs in a metal circuit while the circuit is in operation, as opposed to a failure occurring during fabrication. Electromigration can lead to the formation of voids in the conductor. A void may accumulate and/or grow to a size where the immediate cross-section of the conductor is insufficient to support the quantity of current passing through the conductor, and may also lead to an open circuit. The area of conductor available to conduct heat therealong likewise decreases where the void forms, increasing the risk of conductor failure. This problem is sometimes overcome by doping aluminum with copper and with tight texture or crystalline structure control of the material. However, electromigration in aluminum becomes increasingly problematic as the current density increases.
Copper and its alloys have lower resistivity than aluminum and higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a choice metal for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into high aspect ratio features are limited. Precursors for CVD deposition of copper are ill-developed and involve complex and costly chemistry. Physical vapor deposition into such features produces unsatisfactory results because of limitations in ‘step coverage’ and voids formed in the features.
As a result of these process limitations, electroplating, which had previously been limited to the fabrication of patterns on circuit boards, is just now emerging as a method to fill vias and contacts on semiconductor devices. FIGS. 1A-1E illustrate a metallization technique for forming a dual damascene interconnect in a dielectric layer having dual damascene via and wire definition, wherein the via has a floor exposing an underlying layer. Although a dual damascene structure is illustrated, this method can be applied also to metallize other interconnect features. The method generally comprises physical vapor depositing a barrier layer over the feature surfaces, physical vapor depositing a conductive metal seed layer, preferably copper, over the barrier layer, and then electroplating a conductive metal over the seed layer to fill the structure/feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Referring to FIGS. 1A through 1E, a cross sectional diagram of a layered structure 10 is shown including a dielectric layer 16 formed over an underlying layer 14 which contains electrically conductive features 15. The underlying layer 14 may take the form of a doped silicon substrate or it may be a first or subsequent conducting layer formed on a substrate. The dielectric layer 16 is formed over the underlying layer 14 in accordance with procedures known in the art such as dielectric CVD to form a part of the overall integrated circuit. Once deposited, the dielectric layer 16 is patterned and etched to form a dual damascene via and wire definition, wherein the via has a floor 30 exposing a small portion of the conducting feature 15. Etching of the dielectric layer 16 can be accomplished with various generally known dielectric etching processes, including plasma etching.
Referring to FIG. 1A, a cross-sectional diagram of a dual damascene via and wire definition formed in the dielectric layer 16 is shown. The via and wire definition facilitates the deposition of a conductive interconnect that will provide an electrical connection with the underlying conductive feature 15. The definition provides vias 32 having via walls 34 and a floor 30 exposing at least a portion of the conductive feature 15, and trenches 17 having trench walls 38.
Referring to FIG. 1B, a barrier layer 20 of tantalum or tantalum nitride (TaN) is deposited on the via and wire definition, such that aperture 18 remains in the via 32, by using reactive physical vapor deposition, i.e., by sputtering a tantalum target in a nitrogen/argon plasma. Preferably, where the aspect ratio of the aperture is high (e.g. 4:1 or higher) with a sub-micron wide via, the Ta/TaN is deposited in a high density plasma environment, wherein the sputtered deposition of the Ta/TaN is ionized and drawn perpendicularly to the substrate by a negative bias on the substrate. The barrier layer is preferably formed of tantalum or tantalum nitride, however other barrier layers such as titanium, titanium nitride and combinations thereof may also be used. The process used may be PVD, CVD, or combined CVD/PVD for texture and film property improvement. The barrier layer limits the diffusion of copper into the semiconductor substrate and the dielectric layer and thereby dramatically increases the reliability of the interconnect. It is preferred that the barrier layer has a thickness between about 25 Å and about 400 Å, most preferably about 100 Å.
Referring to FIG. 1C, a PVD copper seed layer 21 is deposited over the barrier layer 20. Other metals, particularly noble metals, can also be used for the seed layer. The PVD copper seed layer 21 provides good adhesion for subsequently deposited metal layers, as well as a conformal layer for even growth of the copper thereover.
Referring to FIG. 1D, a copper layer 22 is electroplated over the PVD copper seed layer 21 to completely fill the via 32 with a copper plug 19.
Referring to FIG. 1E, the top portion of the structure 10, i.e., the exposed copper is then planarized, preferably by chemical mechanical polishing (CMP). During the planarization process, portions of the copper layer 22, copper seed layer 21, barrier layer 20, and dielectric layer 16 are removed from the top surface of the structure, leaving a fully planar surface with conductive interconnect 39.
Metal electroplating in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on wafer-based substrates involve a fountain configuration. The substrate is positioned with the plating surface at a fixed distance above a cylindrical electrolyte container, and the electrolyte impinges perpendicularly on the substrate plating surface. The substrate is the cathode of the plating system, such that ions in the plating solution deposit on the conductive exposed surface of the substrate and the micro-sites on the substrate. However, a number of obstacles impair consistent reliable electroplating of copper onto substrates having a sub-micron scale, high aspect ratio features. Generally, these obstacles involve difficulty with providing uniform current density distribution across the substrate plating surface, which is needed to form a metal layer having uniform thickness. A primary obstacle is how to get current to the substrate and how to ensure that the current is uniformly distributed thereon.
One current method for providing power to the plating surface uses contacts (e.g., pins, ‘fingers’, or springs) which contact the substrate seed layer. The contacts touch the seed layer as close as practically possible to the edge of the substrate, to minimize the wasted area on the wafer due to the presence of the contacts. The ‘excluded’ area can no longer be used to ultimately form devices on the substrate. However, the contact resistance of the contacts to the seed layer may vary from contact to contact, resulting in a non-uniform distribution of current densities across the substrate. Also, the contact resistance at the contract to seed layer interface may vary from substrate to substrate, resulting in inconsistent plating distribution between different substrates using the same equipment. Furthermore, the plating rate tends to be higher near the region of the contacts and be lower at regions remote from the contacts due to the resistivity of the thin seed layer that has been deposited on the substrate. A fringing effect of the electrical field also occurs at the edge of the substrate due to the highly localized electrical field formed at the edge of the plated region, causing a higher deposition rate near the edge of the substrate.
A resistive substrate effect is usually pronounced during the initial phase of the electroplating process and reduces the deposition uniformity because the seed layer and the electroplated layers on the substrate deposition surface are typically thin. The metal plating tends to concentrate near the current feed contacts, i.e., the plating rate is greatest adjacent the contacts, because the current density across the substrate decreases as the distance from the current feed contacts increases due to insufficient conductive material on the seed layer to provide a uniform current density across the substrate plating surface. As the deposition film layer becomes thicker due to the plating, the resistive substrate effect diminishes because a sufficient thickness of deposited material becomes available across the substrate plating surface to provide uniform current densities across the substrate. It is desirable to reduce the resistive substrate effect during electroplating.
Traditional fountain plater designs also provide non-uniform flow of the electrolyte across the substrate plating surface, which compounds the effects of the non-uniform current distribution on the plating surface by providing non-uniform replenishment of plating ions and where applicable, plating additives, across the substrate, resulting in non-uniform plating. The electrolyte flow uniformity across the substrate can be improved by rotating the substrate at a high rate during the plating process. Such rotation introduces complexity into the plating cell design due to the need to furnish current across and revolving interface. However, the plating uniformity still deteriorates at the boundaries or edges of the substrate because of the fringing effects of the electrical field near the edge of the substrate, the seed layer resistance and the potentially variable contact resistance.
There is also a problem in maintaining an electroplating solution to the system having consistent properties over the duration of a plating cycle and/or over a run of multiple wafers being plated. Traditional fountain plater designs generally require continual replenishing of the metal being deposited into the electrolyte. The metal electrolyte replenishing scheme is difficult to control and causes build-up of co-ions in the electrolyte, resulting in difficult to control variations in the ions concentration in the electrolyte. Thus, the electroplating process produces inconsistent results because of inconsistent ion concentration in the electrolyte.
Additionally, operation of a plating cell incorporating a non-consumable anode may cause bubble-related problems because oxygen evolves on the anode during the electroplating process. Bubble-related problems include plating defects caused by bubbles that reach the substrate plating surface and prevent adequate electrolyte contact with the plating surface. It is desirable to eliminate or reduce bubble formation from the system and to remove formed bubbles from the system.
Therefore, there remains a need for a reliable, consistent metal electroplating apparatus and method to deposit uniform, high quality metal layers on substrates to form sub-micron features. There is also a need to form metal layers on substrates having micron-sized, high aspect ratio features to fill the features without voids in the features.